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DATA SHEET
MOS INTEGRATED CIRCUIT
PD43256B
256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT
Description
The PD43256B is a high speed, low power, and 262, 144 bits (32,768 words by 8 bits) CMOS static RAM. Battery backup is available (L, LL, A, and B versions). And A and B versions are wide voltage operations. The PD43256B is packed in 28-pin plastic DIP, 28-pin plastic SOP and 28-pin plastic TSOP (I).
Features
* 32,768 words by 8 bits organization * Fast access time: 70, 85, 100, 120, 150 ns (MAX.) * Wide voltage range (A version: VCC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V) * 2 V data retention * OE input for easy application
Operating supply voltage V 4.5 to 5.5 Operating temperature C 0 to 70 Standby supply current A (MAX.) 50 15 3.0 to 5.5 2.7 to 5.5 Data retention supply currentNote 1 A (MAX.) 3 2
Part number
Access time ns (MAX.) 70, 85 70, 85 85, 100Note 2, 120Note 2
PD43256B-L PD43256B-LL PD43256B-A PD43256B-BNote 2
100, 120, 150
Notes 1. TA 40 C, VCC = 3 V 2. Access time : 85 ns (MAX.) (VCC = 4.5 to 5.5 V)
Version X and P
This data sheet can be applied to the version X and P. Each version is identified with its lot number. Letter X in the fifth character position in a lot number signifies version X, letter P, version P.
JAPAN
D43256B
Lot number
The information in this document is subject to change without notice.
Document No. M10770EJ9V0DS00 (9th edition) Date Published May 1997 N Printed in Japan
The mark
shows major revised points.
(c)
1990, 1993, 1994
PD43256B
Ordering Information
Operating supply voltage V 4.5 to 5.5 Operating temperature C 0 to 70
Part number
Package
Access time ns (MAX.) 70 85 70 85
Remark
PD43256BCZ-70L PD43256BCZ-85L PD43256BCZ-70LL PD43256BCZ-85LL PD43256BGU-70L PD43256BGU-85L PD43256BGU-70LL PD43256BGU-85LL PD43256BGU-A85 PD43256BGU-A10 PD43256BGU-A12 PD43256BGU-B10 PD43256BGU-B12 PD43256BGU-B15 PD43256BGW-70LL-9JL PD43256BGW-85LL-9JL PD43256BGW-A85-9JL PD43256BGW-A10-9JL PD43256BGW-A12-9JL PD43256BGW-B10-9JL PD43256BGW-B12-9JL PD43256BGW-B15-9JL PD43256BGW-70LL-9KL PD43256BGW-85LL-9KL PD43256BGW-A85-9KL PD43256BGW-A10-9KL PD43256BGW-A12-9KL PD43256BGW-B10-9KL PD43256BGW-B12-9KL PD43256BGW-B15-9KL
28-pin plastic DIP (600 mil)
L Version
LL Version
28-pin plastic SOP (450 mil)
70 85 70 85 85 100 120 100 120 150 2.7 to 5.5 3.0 to 5.5
L Version
LL Version
A Version
B Version
28-pin plastic TSOP (I) (8 x 13.4 mm) (Normal bent)
70 85 85 100 120 100 120 150
4.5 to 5.5
LL Version
3.0 to 5.5
A Version
2.7 to 5.5
B Version
28-pin plastic TSOP (I) (8 x 13.4 mm) (Reverse bent)
70 85 85 100 120 100 120 150
4.5 to 5.5
LL Version
3.0 to 5.5
A Version
2.7 to 5.5
B Version
2
PD43256B
Pin Configuration (Marking Side)
28-pin plastic DIP (600 mil) PD43256BCZ 28-pin plastic SOP (450 mil) PD43256BGU
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4
A0 - A14 CS WE OE VCC GND
: Address inputs : Chip Select : Write Enable : Output Enable : Power supply : Ground
I/O1 - I/O8 : Data inputs/outputs
3
PD43256B
28-pin plastic TSOP (I) (8 x 13.4 mm) (Normal bent)
PD43256BGW-9JL
OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2
28-pin plastic TSOP (I) (8 x 13.4 mm) (Reverse bent)
PD43256BGW-9KL
A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3
4
PD43256B
Block Diagram
Address buffer
A0 | A14
Row decoder
Memory cell array 262,144 bits
I/O1 | I/O8
Input data controller
Sense/Switch
Output data controller
Column decoder
Address buffer
CS
OE
WE VCC GND
Truth Table
CS H L L L OE x H x L WE x H L H Mode Not selected Output disable Write Read DIN DOUT I/O High impedance Supply current ISB ICCA
Remark x: Don't care
5
PD43256B
Electrical Characteristics
Absolute Maximum Ratings
Parameter Supply voltage Input/Output voltage Operating ambient temperature Storage temperature Symbol VCC VT TA Tstg Rating -0.5 Note to +7.0 -0.5 Note to VCC + 0.5 0 to 70 -55 to +125 Unit V V C C
Note
-3.0 V (MIN.) (Pulse width 50 ns)
Caution Exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational sections of this characteristics. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions
PD43256B-L PD43256B-LL
MIN. Supply voltage High level input voltage Low level input voltage Operating ambient temperature VCC VIH VIL TA 4.5 2.2 -0.3 Note 0 MAX. 5.5 VCC + 0.5 +0.8 70
PD43256B-A
MIN. 3.0 2.2 -0.3 Note 0 MAX. 5.5 VCC + 0.5 +0.5 70
PD43256B-B
Unit MIN. 2.7 2.2 -0.3 Note 0 MAX. 5.5 VCC + 0.5 +0.5 70 V V V C
Parameter
Symbol
Note
-3.0 V (MIN.) (Pulse width 50 ns)
6
PD43256B
DC Characteristics (Recommended operating conditions unless otherwise noted) (1/2)
PD43256B-L
Parameter Input leakage current I/O leakage current Symbol ILI ILO Test conditions VIN = 0 V to VCC VI/O = 0 V to VCC OE = VIH or CS = VIH or WE = VIL CS = VIL, Minimum cycle time, II/O = 0 mA CS = VIL, II/O = 0 mA CS 0.2 V, Cycle = 1 MHz, II/O = 0 mA VIL 0.2 V, VIH VCC - 0.2 V CS = VIH CS VCC - 0.2 V IOH = -1.0 mA IOH = -0.1 mA IOL = 2.1 mA 2.4 VCC-0.5 0.4 1.0
PD43256B-LL
Unit
MIN. TYP. MAX. MIN. TYP. MAX. -1.0 -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 +1.0
A A
mA
Operating supply current
ICCA1
45
45
ICCA2 ICCA3
10 10
10 10
Standby supply current
ISB ISB1
3 50 2.4 VCC-0.5 0.5
3 15
mA
A
V
High level output voltage
VOH1 VOH2
Low level output voltage
VOL
0.4
V
Remarks 1. VIN: Input voltage 2. These DC Characteristics are in common regardless of package types.
7
PD43256B
DC Characteristics (Recommended operating conditions unless otherwise noted) (2/2)
PD43256B-A
Parameter Input leakage current I/O leakage current Symbol ILI ILO Test conditions VIN = 0 V to VCC VI/O = 0 V to VCC CS = VIH or WE = VIL or OE = VIH CS = VIL, PD43256B-A85 Minimum cycle time, PD43256B-A10 II/O = 0 mA PD43256B-A12
PD43256B-B
Unit
MIN. TYP. MAX. MIN. TYP. MAX. -1.0 -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 +1.0
A A
mA
Operating supply current
ICCA1
45
--
PD43256B-B10 PD43256B-B12 PD43256B-B15
VCC 3.3 V ICCA2 CS = VIL, II/O = 0 mA VCC 3.3 V ICCA3 CS 0.2 V, Cycle = 1 MHz, II/O = 0 mA, VIL 0.2 V, VIH VCC - 0.2 V Standby supply current ISB CS = VIH VCC 3.3 V ISB1 CS VCC - 0.2 V VCC 3.3 V High level output voltage VOH1 IOH = -1.0 mA, VCC 4.5 V IOH = -0.5 mA, VCC < 4.5 V VOH2 IOH = -0.1 mA IOH = -0.02 mA Low level output voltage VOL IOL = 2.1 mA, VCC 4.5 V IOL = 1.0 mA, VCC < 4.5 V VOL1 IOL = 0.02 mA 2.4 2.4 -- VCC-0.1 0.5 VCC 3.3 V
--
45
-- 10 -- 10
20 10 5 10
-- 3 -- 15 -- 2.4 2.4 -- VCC-0.1 0.4 0.4 0.1 0.5 0.5
5 3 2 15 10 V mA
A
0.4 0.4 0.1
V
Remarks 1. VIN: Input voltage 2. These DC characteristics are in common regardless of package types.
Capacitance (TA = 25 C, f = 1 MHz)
Parameter Input capacitance Input/Output capacitance Symbol CIN CI/O VIN = 0 V VI/O = 0 V Test conditions MIN. TYP. MAX. 5 8 Unit pF pF
Remarks 1. VIN: Input voltage 2. These parameters are periodically sampled and not 100 % tested.
8
PD43256B
AC Characteristics (Recommended operating conditions unless otherwise noted)
AC Test Conditions Input waveform (Rise/fall time 5 ns) Input pulse levels 0.8 V to 2.2 V: PD43256B-L, 43256B-LL 0.5 V to 2.2 V: PD43256B-A, 43256B-B
1.5 V
Test points
1.5 V
Output waveform
1.5 V
Test points
1.5 V
Output load
PD43256B-A, 43256B-B : 1TTL + 100 pF PD43256B-L, 43256B-LL:
AC characteristics with notes should be measured with the output load shown in Figure 1 and Figure 2. Figure 1 (For tAA, tACS, tOE, tOH)
+5 V
Figure 2 (For tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW)
+5 V
1.8 k
1.8 k
I/O (Output)
I/O (Output)
990
100 pF CL
990
5 pF CL
Remark
CL includes capacitances of the probe and jig, and stray capacitances.
9
PD43256B
Read Cycle (1/2)
VCC 4.5 V
Parameter
Symbol
PD43256B-70
MIN. MAX.
PD43256B-85 PD43256B-A85/A10/A12 PD43256B-B10/B12/B15
MIN. 85 MAX.
Unit Condition
Read cycle time Address access time CS access time OE access time Output hold from address change CS to output in low impedance OE to output in low impedance CS to output in high impedance OE to output in high impedance
tRC tAA tACS tOE tOH tCLZ tOLZ tCHZ tOHZ
70 70 70 35 10 10 5 30 30
ns 85 85 40 ns ns ns ns ns ns 30 30 ns ns Note 2 Note 1
10 10 5
Notes 1. See the output load shown in Figure 1 except for PD43256B-A, 43256B-B. 2. See the output load shown in Figure 2 except for PD43256B-A, 43256B-B. Remark These AC characteristics are in common regardless of package types and L, LL versions. Read Cycle (2/2)
VCC 3.0 V Parameter VCC 2.7 V
Symbol PD43256B-A85 PD43256B-A10 PD43256B-A12 PD43256B-B10 PD43256B-B12 PD43256B-B15 Unit MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Condition
Read cycle time Address access time CS access time OE access time Output hold from address change CS to output in low impedance OE to output in low impedance CS to output in high impedance OE to output in high impedance
tRC tAA tACS tOE tOH tCLZ tOLZ tCHZ tOHZ
85 85 85 50 10 10 5 35 35
100 100 100 60 10 10 5 35 35
120 120 120 60 10 10 5 40 40
100 100 100 60 10 10 5 35 35
120 120 120 60 10 10 5 40 40
150
ns 150 ns Note 150 ns 70 ns ns ns ns 50 50 ns ns
10 10 5
Note Loading condition is 1TTL + 100 pF. Remark These AC characteristics are in common regardless of package types and L, LL versions.
10
PD43256B
Read Cycle Timing Chart
tRC Address (Input) tAA tACS CS (Input) tCLZ OE (Input) tOE tOLZ I/O (Output) High impedance Data out High impedance tOHZ tCHZ tOH
Remark
In read cycle, WE should be fixed to high level.
11
PD43256B
Write Cycle (1/2)
VCC 4.5 V
Parameter
Symbol
PD43256B-70
MIN. MAX.
PD43256B-85 PD43256B-A85/A10/A12 PD43256B-B10/B12/B15
MIN. 85 70 70 60 35 0 0 0 MAX.
Unit Condition
Write cycle time CS to end of write Address valid to end of write Write pulse width Data valid to end of write Data hold time Address setup time Write recovery time WE to output in high impedance Output active from end of write
tWC tCW tAW tWP tDW tDH tAS tWR tWHZ tOW
70 50 50 55 30 0 0 0 30 10
ns ns ns ns ns ns ns ns 30 ns ns Note
10
Note See the output load shown in Figure 2 except for PD43256B-A, 43256B-B. Remark These AC characteristics are in common regardless of package types and L, LL versions. Write Cycle (2/2)
VCC 3.0 V Parameter VCC 2.7 V Condition
Symbol PD43256B-A85 PD43256B-A10 PD43256B-A12 PD43256B-B10 PD43256B-B12 PD43256B-B15 Unit MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Write cycle time CS to end of write Address valid to end of write Write pulse width Data valid to end of write Data hold time Address setup time Write recovery time WE to output in high impedance Output active from end of write
tWC tCW tAW tWP tDW tDH tAS tWR tWHZ tOW
85 70 70 60 60 0 0 0 30 10
100 70 70 60 60 0 0 0 35 10
120 90 90 80 70 0 0 0 40 10
100 70 70 60 60 0 0 0 35 10
120 90 90 80 70 0 0 0 40 10
150 100 100 90 80 0 0 0 50 10
ns ns ns ns ns ns ns ns ns Note ns
Note Loading condition is 1TTL + 100 pF. Remark These AC characteristics are in common regardless of package types and L, LL versions.
12
PD43256B
Write Cycle Timing Chart 1 (WE Controlled)
tWC Address (Input) tCW CS (Input) tAW tAS WE (Input) tOW tWHZ I/O (Input/Output) Indefinite data out High impedance tDW Data in tDH High impedance Indefinite data out tWP tWR
Cautions 1. CS or WE should be fixed to high level during address transition. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remarks 1. Write operation is done during the overlap time of a low level CS and a low level WE. 2. When WE is at low level, the I/O pins are always high impedance. When WE is at high level, read operation is executed. Therefore OE should be at high level to make the I/O pins high impedance. 3. If CS changes to low level at the same time or after the change of WE to low level, the I/O pins will remain high impedance state.
13
PD43256B
Write Cycle Timing Chart 2 (CS Controlled)
tWC Address (Input)
tAS CS (Input) tAW tWP WE (Input)
tCW
tWR
tDW High impedance I/O (Input) Data In
tDH High impedance
Cautions 1. CS or WE should be fixed to high level during address transition. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remark Write operation is done during the overlap time of a low level CS and a low level WE.
14
PD43256B
Low VCC Data Retention Characteristics L Version (PD43256B-L: TA = 0 to 70 C)
Parameter Symbol Test conditions CS VCC - 0.2 V VCC = 3.0 V, CS VCC - 0.2 V 0 MIN. 2.0 0.5 TYP. MAX. 5.5 20 Note Unit V
Data retention supply voltage VCCDR Data retention supply current Chip deselection to data retention mode Operation recovery time ICCDR tCDR
A
ns
tR
5
ms
Note 3 A (TA 40 C)
LL Version (PD43256B-LL: TA = 0 to 70 C) A Version (PD43256B-A: TA = 0 to 70 C) B Version (PD43256B-B: TA = 0 to 70 C)
Parameter Data retention supply voltage Data retention supply current Chip deselection to data retention mode Operation recovery time Symbol VCCDR ICCDR tCDR Test conditions CS VCC - 0.2 V VCC = 3.0 V, CS VCC - 0.2 V 0 MIN. 2.0 0.5 TYP. MAX. 5.5 7 Note Unit V
A
ns
tR
5
ms
Note 2 A (TA 40 C), 1 A (TA 25 C)
15
PD43256B
Data Retention Timing Chart
tCDR 5.0 V 4.5 V
Note
Data retention mode
tR
VCC
CS VIH (MIN.) VCCDR CS VCC - 0.2 V VIL (MAX.)
GND
Note
A Version: 3.0 V, B Version: 2.7 V
Remark The other pins (address, OE, WE, I/Os) can be in high impedance state.
16
PD43256B
Package Drawings
28 PIN PLASTIC DIP (600 mil)
28 15
1 A
14
K L
J
I
G
H
F D N
M
C
B
M
R
NOTES 1) Each lead centerline is located within 0.25 mm (0.01 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM MILLIMETERS A B C D F G H I J K L M N R 38.10 MAX. 2.54 MAX. 2.54 (T.P.) 0.500.10 1.2 MIN. 3.60.3 0.51 MIN. 4.31 MAX. 5.72 MAX. 15.24 (T.P.) 13.2 0.25 +0.10 -0.05 0.25 0 ~ 15 INCHES
1.500 MAX. 0.100 MAX. 0.100 (T.P.) +0.004 0.020 -0.005 0.047 MIN. 0.1420.012 0.020 MIN. 0.170 MAX. 0.226 MAX. 0.600 (T.P.) 0.520
0.010 +0.004 -0.003
0.01 0 ~ 15
P28C-100-600A1-1
17
PD43256B
28 PIN PLASTIC SOP (450 mil)
28
15
detail of lead end
1 A
G
14 H I J
F
E
C D M
M
N
B
K
L
NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS A B C D E F G H I J K L M N P 19.05 MAX. 1.27 MAX. 1.27 (T.P.) 0.400.10 0.20.1 3.0 MAX. 2.550.1 11.80.3 8.40.1 1.70.2 0.20 +0.07 -0.03 0.70.2 0.12 0.10 55
P
INCHES 0.750 MAX. 0.050 MAX. 0.050 (T.P.) 0.016 +0.004 -0.005 0.0080.004 0.119 MAX. 0.100 +0.005 -0.004 0.465 +0.012 -0.013 0.331 +0.004 -0.005 0.0670.008 0.008 +0.003 -0.002 0.028 +0.008 -0.009 0.005 0.004 55 P28GU-50-450A-1
18
PD43256B
28PIN PLASTIC TSOP ( I ) (8x13.4)
1
28
detail of lead end
S R
14
15
Q
P I J A G
H L K
NOTE (1) Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. (2) "A" excludes mold flash. (Includes mold flash : 8.4mm MAX. <0.331 inch MAX.>)
C N D M
M
B
ITEM MILLIMETERS A 8.00.1 B C D G H I J K L M N P Q R S 0.6 MAX. 0.55 (T.P.) 0.22 +0.08 -0.07 1.0 12.40.2 11.80.1 0.80.2
INCHES 0.3150.004 0.024 MAX. 0.022 (T.P.) 0.0090.003 0.039 0.4880.008 0.465 +0.004 -0.005 0.031 +0.009 -0.008
0.145 +0.025 0.0060.001 -0.015 0.50.1 0.08 0.10 13.40.2 0.10.05 3 +7 -3 1.2 MAX. 0.020 +0.004 -0.005 0.003 0.004 0.528 +0.008 -0.009 0.0040.002 3 +7 -3 0.048 MAX. P28GW-55-9JL-1
19
PD43256B
28PIN PLASTIC TSOP ( I ) (8x13.4)
1
28
detail of lead end Q R S
14
15
K H
N L
D
M
M
C
B
G I P J A
NOTE (1) Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. (2) "A" excludes mold flash. (Includes mold flash : 8.4mm MAX. <0.331 inch MAX.>)
ITEM MILLIMETERS A 8.00.1 B C D G H I J K L M N P Q R S 0.6 MAX. 0.55 (T.P.) 0.22 +0.08 -0.07 1.0 12.40.2 11.80.1 0.80.2
INCHES 0.3150.004 0.024 MAX. 0.022 (T.P.) 0.0090.003 0.039 0.4880.008 0.465 +0.004 -0.005 0.031 +0.009 -0.008
0.145 +0.025 0.0060.001 -0.015 0.50.1 0.08 0.10 13.40.2 0.10.05 3 +7 -3 1.2 MAX. 0.020 +0.004 -0.005 0.003 0.004 0.528 +0.008 -0.009 0.0040.002 3 +7 -3 0.048 MAX. P28GW-55-9KL-1
20
PD43256B
Recommended Soldering Conditions
The following conditions (See table below) must be met when soldering PD43256B. For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). Please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions.
Types of Surface Mount Device
PD43256BGU: 28-pin plastic SOP (450 mil) PD43256BGW-9JL: 28-pin plastic TSOP (I) (8 x 13.4 mm) (Normal bent) PD43256BGW-9KL: 28-pin plastic TSOP (I) (8 x 13.4 mm) (Reverse bent)
Please consult with our sales offices.
Type of Through Hole Mount Device
PD43256BCZ: 28-pin plastic DIP (600 mil)
Soldering process Wave soldering (only to leads) Partial heating method Soldering conditions Solder temperature: 260 C or below, Flow time: 10 seconds or below Terminal temperature: 300 C or below, Time: 3 seconds or below (Per one lead)
Caution Do not jet molten solder on the surface of package.
21
PD43256B
[MEMO]
22
PD43256B
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
23
PD43256B
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5
2

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